……和 Hanna - Ricardo Jasinski 写的《Effective Coding with VHDL: Principles and Best Practices》（我正在用这本书理清在 VHDL 中实现各种功能的途径，并在代码中落实最佳实践。） - Andrew Rushton 写的《VHDL for Logic Synthesis》 - Pong Chu 写的《FPGA Prototyping by VHDL Examples: Xilinx MicroBlaze MCS SoC》
…and Hanna - Effective Coding with VHDL: Principles and Best Practices by Ricardo Jasinski (I'm using this to sort through the various ways to do things in VHDL and have best practices in my code.) - VHDL for Logic Synthesis by Andrew Rushton - FPGA Prototyping by VHDL Examples: Xilinx MicroBlaze MCS SoC by Pong Chu
……出于好意，并不是想吵架…… --- 你的代码里有些小问题，表明你可能习惯用 verilog/SV，而不是个有经验的 VHDL 老手。请去读读 Andrew Rushton 的《VHDL for Logic Synthesis》。我也建议你去了解一下 VHDL 的 9 值逻辑（9-valued logic），为什么会这样设计，以及它和 verilog 的 Bit 有何不同。
…intentions, not trying to start a fight... --- There are some minor issues with your code that shows you are probably a verilog/SV guy and not an experienced VHDL guy. Please read Andrew Rushtons "VHDL for Logic Synthesis". I also recommend you read on VHDLs 9-valued logic and why it was designed this way and how it differs from verilogs Bit.
……和 Hanna - Ricardo Jasinski 写的《Effective Coding with VHDL: Principles and Best Practices》（我正在用这本书理清在 VHDL 中实现各种功能的途径，并在代码中落实最佳实践。） - Andrew Rushton 写的《VHDL for Logic Synthesis》 - Pong Chu 写的《FPGA Prototyping by VHDL Examples: Xilinx MicroBlaze MCS SoC》
…and Hanna - Effective Coding with VHDL: Principles and Best Practices by Ricardo Jasinski (I'm using this to sort through the various ways to do things in VHDL and have best practices in my code.) - VHDL for Logic Synthesis by Andrew Rushton - FPGA Prototyping by VHDL Examples: Xilinx MicroBlaze MCS SoC by Pong Chu
……出于好意，并不是想吵架…… --- 你的代码里有些小问题，表明你可能习惯用 verilog/SV，而不是个有经验的 VHDL 老手。请去读读 Andrew Rushton 的《VHDL for Logic Synthesis》。我也建议你去了解一下 VHDL 的 9 值逻辑（9-valued logic），为什么会这样设计，以及它和 verilog 的 Bit 有何不同。
…intentions, not trying to start a fight... --- There are some minor issues with your code that shows you are probably a verilog/SV guy and not an experienced VHDL guy. Please read Andrew Rushtons "VHDL for Logic Synthesis". I also recommend you read on VHDLs 9-valued logic and why it was designed this way and how it differs from verilogs Bit.